The Heirloom Development Tools provide yacc, lex, m4, make, and SCCS as portable derivatives of the utilities released by Sun as part of OpenSolaris. The OpenSolaris utilities were in turn derived from the original Unix versions, and are assumed be conforming implementations of the POSIX standard.
xtcc is a set of tools being developed for market research data processing. It is comprised of the following components: xtcc compiler, a data processing backend, qscript, a questionnaire scripting language, a data conversion program for converting data from the qscript format to data processing backend format, and dpassist, a tool to aid in the writing of tabulation and edit specs. The input for this program will be the questionnaire script or map file for the data.
A parsing toolkit that supports both top-down (LL(1) and Simple Precedence) and bottom-up parsing (LR(0), SLR(1), LR(1) and LALR(1)). The toolkit also supports generating Java parsers for all the bottom-up parsing methods, based on a CUP definition (similar to Yacc and CUP, but not restricted to LALR parsers only).
yagg, given YACC-like and LEX-like input files, generates a C++ program that generates all strings of a user-specified length. This program can then be used to generate inputs for testing, or to validate that a grammar accepts the strings that you think it does. The grammar file provides the grammar productions for string generation, along with optional action blocks that can perform context-sensitive checks in order to limit the generated strings. The LEX-like terminal generator file provides specifications that instruct the program how to generate strings for terminals in the grammar.
links2world Firewall is an iptables script generator for Linux 2.4.x or newer kernels. The configuration file is very human readable and easy to understand and write. It does not matter if you have one, two, three, or twenty network interfaces; it is able to generate stateful iptables rule sets that control the packet flows between all the networks your machine is attached to.
Alliance CAD System is a set of EDA tools and portable cell libraries for VLSI design. It covers a wide range of the standard design flow (from VHDL up to layout). It includes a VHDL simulator, RTL synthesis tools, place and route tools, netlist extractor, DRC, and a layout editor.