Open Broadcast Encoder (OBE) allows you to replace expensive hardware broadcast encoders with low-cost commodity hardware. Powered by the high quality x264 encoder, you can have full control over your encode chain with compatibility with all industry standards and practices. OBE can handle all your Video-on-Demand and realtime needs.
Resize Magic is an application that resizes images with a high quality algorithm, similar to the Lanczos algorithm used by other programs, with some modifications. It can be used to batch resize images, and preserves Exif data and ICC color profiles. A Photoshop plugin is also available as a commercial product.
Peg Solitaire is a board game played with pegs: in the classic mode, the board has 33 positions and 32 tokens because the center position is without form. The objective of Peg Solitaire is to remove the pegs but only with horizontal and vertical movements. It is also known as English peg solitaire or Senku. In the reverse modes, initially there is only one piece on the board.
The Kowalski project aims to provide a data driven, lightweight cross platform audio solution. The target audience is developers of games and similar applications where real time audio plays an important role. The Kowalski engine, which is the runtime component, relies only on host-specific external libraries to pass the final output buffers to the audio hardware. All other processing is done in the engine code. Features include positional audio (distance attenuation, cone attenuation, Doppler shift, binaural panning), real time Ogg Vorbis decoding, a powerful mix bus system, and tools to build, validate, and view Kowalski data.
CoreTML framework is a template configuration system. It is based on the idea of parametrized templates that are created by inserting special content into source code files. These templates can later be used to generate output files depending upon parameters chosen by the user. CoreTML framework was created primarily to provide a platform for the design and deployment of semiconductor IP cores on a hardware description language (HDL) level (i.e. VHDL or Verilog).