Sigasi is an intelligent Eclipse- based development environment (IDE) for the VHDL language. It contains an ultra-fast VHDL parser and compiler that runs transparently in the background. At any given moment as you make modifications, the tool fully understands the design in terms of VHDL concepts. It allows you to write code faster by providing intelligent code completion, instant error reporting, intelligent navigation, mouse-over descriptions, a hierarchy browser, version control, issue and time tracking, and project and code templates.
rgbproc-repository is intended for use with Xilinx EDK tools. It consists of many units written in VHDL that can be used to build a design for image/video processing. The backbone is the data bus (called simply RGB) that is used to pass data (typically) from VGA input to VGA/DVI output.
Controlix is a control theory based operating system. It abstracts the complete abstraction hierarchy of computer systems principles, from basic signal-on-wire all the way up to abstract libraries and interface linkage. It is written in the VHDL language and is designed to be modular, synchronous, and retargetable.
TTA-based Co-design Environment (TCE) is a toolset that provides a complete co-design flow from C programs down to synthesizable VHDL and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network.
Chips is a Python library for designing hardware devices that provides a high-level device modelling language. Native simulations integrate with Python so you can use Python extension modules such as Scipy, Numpy, Matplotlib, and PIL to provide a rich verification environment. Device models can be automatically translated into synthesizable VHDL, and highly optimized soft-processors are generated for an efficient implementation. A plugin mechanism is provided so that additional code generators can be added. C++ and Graphviz plugins are provided. Existing VHDL IP can be imported, and seamless co-simulation of C++ and VHDL outputs is is supported.