Screen Message displays a given multi-line message as large as possible, fullscreen and black on white. You can specify the text when launching sm, or edit it while the program is running. It is useful to send messages across a room (e.g., during a university lecture). For fast startup, it is recommended that you bind it to a key in your Desktop Environment.
Novius OS is a CMS that takes up the challenge of managing Web content in today’s multi-channel environment. Its goal is to provide users with one single tool for their digital communication: Web sites, social networks, mobile applications, email, and custom business applications. It is based on the FuelPHP framework. It uses an HTML5 interface, the jQuery UI framework, and the Wijmo and TinyMCE plugins.
MapReduce-BitDew is an implementation of the MapReduce programming model proposed by Google for Internet Desktop Grids. Using MapReduce-BitDew, you can execute MapReduce applications on resources like Desktop PCs distributed on the Internet. MapReduce-BitDew features a firewall-friendly protocol, fault-tolerance, result-certification, 2-level schedulers, and more.
dwarves is a set of tools to inspect the DWARF debugging information inserted in ELF binaries by compilers such as GCC, and which are used by well-known debuggers such as GDB and more recent ones such as systemtap. With pahole, the struct packing and cacheline efficiency can be inspected.
easy-rsa is a small RSA key management package based on the OpenSSL command line tool. While it is primary concerned with key management for the SSL VPN application space, it can also be used for building Web certificates. It was originally included as part of OpenVPN, but is now a separate project.
System# is a .NET library intended for the description of real-time embedded systems. It comes with a built-in simulator kernel and a code transformation engine that converts a design into synthesizable VHDL. The main focus is currently the development of FPGA designs. System# not only supports register-transfer-level (RTL) descriptions whose translation to VHDL is straightforward, but is also capable of converting clocked threads with wait statements to a synthesizable VHDL state machine. Furthermore, System# introduces synthesizable transaction-level modeling features. From a technological point of view, it uses reflection and assembly code (CIL) decompilation to reconstruct an abstract syntax tree (AST) from the system design. The AST conforms to SysDOM, a document object model for describing component-based reactive systems. An unparsing stage converts the AST to VHDL. The decompilation process can be instrumented in various ways by attribute-based programming. Furthermore, transformations of the AST itself are possible. This enables implementation of advanced features such as converting clocked threads to finite state machines.