Astaro Portscan Detection is a netfilter target which will attempt to detect TCP and UDP port scans and log them to syslog. This target is based upon Solar Designer's scanlogd. It suppports mutliple levels of logging, custom prefixes for entries, weighted total port scan detection, and port scan temporal spread detection.
El Cid is a caller ID program for Linux. It just sits on your modem waiting for something to happen, parses the input, and displays the caller ID information. All records are logged to a file in csv format so you can easily parse it for logging into a database, viewing on the Web via CGI, etc.
Ettercap is a network sniffer/interceptor/logger for ethernet LANs. It supports active and passive dissection of many protocols (even ciphered ones, like SSH and HTTPS). Data injection in an established connection and filtering on the fly is also possible, keeping the connection synchronized. Many sniffing modes were implemented to give you a powerful and complete sniffing suite. Plugins are supported. It has the ability to check whether you are in a switched LAN or not, and to use OS fingerprints (active or passive) to let you know the geometry of the LAN.
iSSL (independant Secure Sockets Layer) is a minimalistic cryptographical API that uses the RSA and AES ciphers to establish SSL-alike, secure encrypted communications between two peers communicating through a network socket, including session key generation and public key exchange.
E-Cell System is an object-oriented software suite for modelling, simulation, and analysis of large scale complex systems such as biological cells. It allows many components, driven by multiple algorithms with different timescales, to coexist. The core library is written in C++ with a Python binding, and frontend software uses Python.
HDLmaker generates hierarchical Verilog and VHDL code, PCB netlists, simulation and synthesis scripts/projects/make files, and schematics. It can translate Verilog/VHDL and HDLmaker projects into HTML, including extensive hyperlinking between the modules. It can also translate PADS PCB netlists into Verilog and VHDL and can do some simple VHDL to Verilog translations. HDLMaker synplifies the development of complex FPGAs and ASICs, and has extensive support for most Xilinx FPGAs.