MongoMongo is an Object-Document-Mapper (ODM) for MongoDB. The philosophy of MongoMongo is to provide a familiar API to Java developers who have been using ActiveORM or Hibernate, while leveraging the power of MongoDB's schemaless and high performance document-based design, dynamic queries, and atomic modifier operations.
libtld is a library used to extract the TLD from a URI. This allows you to extract the exact domain name, sub-domains, and all the TLD (top level, second level, third level, etc.). The problem with TLDs is that you cannot know where the domain starts. Some domains can use one top-level domain, others use two, etc. However, it may be useful to know where the domain is to have the exact list of sub-domains. For example, if you want to force www. at the start of the domain name if no other sub-domains are specified, then you need to know exactly how many TLD are defined in a URI. The libtld offers one function: tld(), which gives you a way to extract the TLD from any URI. The result is the offset where the TLD starts. This gives you enough information to extract everything else you need.
Alore is an object-oriented programming language with a clean syntax that resembles Python and Lua. It is optionally-typed like Google Dart. It is both a dynamic scripting language and a general-purpose language with static typing. It is aimed at most programming tasks, from short scripts to complex applications. It allows programmers to freely mix static and dynamic typing within a program. It has native threads and a very fast edit-test cycle. Programmers can always bypass type checking and run their programs immediately.
Chips is a Python library for designing hardware devices that provides a high-level device modelling language. Native simulations integrate with Python so you can use Python extension modules such as Scipy, Numpy, Matplotlib, and PIL to provide a rich verification environment. Device models can be automatically translated into synthesizable VHDL, and highly optimized soft-processors are generated for an efficient implementation. A plugin mechanism is provided so that additional code generators can be added. C++ and Graphviz plugins are provided. Existing VHDL IP can be imported, and seamless co-simulation of C++ and VHDL outputs is is supported.