1 project tagged "HDL"
Updated 13 Sep 2012
fpgasm
| Pop | 21.10 |
|---|---|
| Vit | 15.91 |
fpgasm creates bare-metal FPGA designs without Verilog or VHDL. Traditionally, FPGAs are built using proprietary Verilog or VHDL language implementations provided by the vendor. fpgasm is to Verilog and VHDL as assembly language is to C++. It takes you all the way to the netlist, and is not just a translator to Verilog. Because of that, the total "make" time to a working fpga is seconds, not minutes. With fewer than ten reserved words, fpgasm syntax can be mastered in a few minutes. With FPGA assembler, you can focus on understanding the FPGA substrate and how your design should map onto it (instead of figuring out large and complicated tools).
