OpenUDID provides a cross-platform method for generating globally unique per-device identifiers. UDIDs are used for analytical or CRM purposes, such as to track how much time users spend in free apps before upgrading to the paid version, or for tracking the source of a download when advertising on an ad network.
Embedded GLIBC (EGLIBC) is a variant of the GNU C Library (GLIBC) which is designed to work well on embedded systems. It strives to be source- and binary-compatible with GLIBC. EGLIBC's goals include a reduced footprint, configurable components, and better support for cross-compilation and cross-testing.
Fix8 is a modern open source C++ FIX framework featuring complete schema driven customisation, high performance, and fast application development. The system is comprised of a compiler for generating C++ message and field encoders, decoders, and instantiation tables, a runtime library to support the generated code and framework, and a set of complete client/server test applications. For the same message, Fix8 encodes 3.2 times faster and decodes 2.3 times faster than Quickfix, an average of 2.7 times. In other words, it reduces encode latency by 69% and reduces decode latency by 56%.
The BEL Framework is a platform designed to overcome many of the challenges associated with capturing, integrating, and storing knowledge within an organization, and sharing the knowledge across the organization and between business partners. Central to the design of the framework is the ability to integrate knowledge across different representational vocabularies and ontologies. This allows organizations to combine knowledge from disparate sources such as existing applications, internal sources, and business partners. It can then be made available through a standardized set of computable networks and APIs.
System# is a .NET library intended for the description of real-time embedded systems. It comes with a built-in simulator kernel and a code transformation engine that converts a design into synthesizable VHDL. The main focus is currently the development of FPGA designs. System# not only supports register-transfer-level (RTL) descriptions whose translation to VHDL is straightforward, but is also capable of converting clocked threads with wait statements to a synthesizable VHDL state machine. Furthermore, System# introduces synthesizable transaction-level modeling features. From a technological point of view, it uses reflection and assembly code (CIL) decompilation to reconstruct an abstract syntax tree (AST) from the system design. The AST conforms to SysDOM, a document object model for describing component-based reactive systems. An unparsing stage converts the AST to VHDL. The decompilation process can be instrumented in various ways by attribute-based programming. Furthermore, transformations of the AST itself are possible. This enables implementation of advanced features such as converting clocked threads to finite state machines.