CoreTML framework is a template configuration system. It is based on the idea of parametrized templates that are created by inserting special content into source code files. These templates can later be used to generate output files depending upon parameters chosen by the user. CoreTML framework was created primarily to provide a platform for the design and deployment of semiconductor IP cores on a hardware description language (HDL) level (i.e. VHDL or Verilog).
fpgatools is a toolchain for programming flexible programmable gate arrays (FPGAs). The only supported chip at this time is the xc6slx9, a cheap (circa $10 U.S.) but powerful 45nm-generation chip with about 2400 LUTs, block ram, and multiply-accumulate devices. The principles of fpgatools are to reach the maximum physical performance of the chip, to provide fast development cycles, to be an independent toolchain which only depends on other Free Software, and to be a lightweight C implementation without a GUI.
fpgasm creates bare-metal FPGA designs without Verilog or VHDL. Traditionally, FPGAs are built using proprietary Verilog or VHDL language implementations provided by the vendor. fpgasm is to Verilog and VHDL as assembly language is to C++. It takes you all the way to the netlist, and is not just a translator to Verilog. Because of that, the total "make" time to a working fpga is seconds, not minutes. With fewer than ten reserved words, fpgasm syntax can be mastered in a few minutes. With FPGA assembler, you can focus on understanding the FPGA substrate and how your design should map onto it (instead of figuring out large and complicated tools).
MBSL (MicroBlaze Simple Linux) is a set of Makefile scripts to create an image of a Linux-based OS for the Xilinx MicroBlaze (FPGA) soft processor. It provides very simple package management that allows you to customize the resulted image. The purpose is to just type 'make build install' and get the configured image.
System# is a .NET library intended for the description of real-time embedded systems. It comes with a built-in simulator kernel and a code transformation engine that converts a design into synthesizable VHDL. The main focus is currently the development of FPGA designs. System# not only supports register-transfer-level (RTL) descriptions whose translation to VHDL is straightforward, but is also capable of converting clocked threads with wait statements to a synthesizable VHDL state machine. Furthermore, System# introduces synthesizable transaction-level modeling features. From a technological point of view, it uses reflection and assembly code (CIL) decompilation to reconstruct an abstract syntax tree (AST) from the system design. The AST conforms to SysDOM, a document object model for describing component-based reactive systems. An unparsing stage converts the AST to VHDL. The decompilation process can be instrumented in various ways by attribute-based programming. Furthermore, transformations of the AST itself are possible. This enables implementation of advanced features such as converting clocked threads to finite state machines.