FeResPost is a library that allows the rapid development of small programs for the post-processing of Nastran or Samcef finite element results. The library allows easy manipulation of finite element models, groups, and results. Efficient post-processing is possible because the time-consuming operations are written in C/C++. The library is distributed as a COM component, a .NET assembly, as well as a Ruby compiled extension.
Image Tools is a screen capture and file sharing tool. It features multi-threaded batch image resizing, conversion, cropping, flipping/rotating, watermarks, decolorizing (grayscale, negative, sepia), and optimizing. The BMP, GIF, TIFF, JPEG, PNG, and EMF image types are supported. It is compatible with MONO (only for GNOME). Multicore processing is supported to increase performance. The quality for output when optimizing is variable. Color channels can be filtered. An internal benchmarking tool is available. Indexed pixel format images can be processed.
SourceAFIS is a fingerprint recognition/matching SDK (library), or more generally an Automated Fingerprint Identification System (AFIS). It essentially compares two fingerprints and decides whether they belong to the same person. It can quickly search a large database of registered fingerprints. It comes with an easy-to-use API (pure .NET and Java) plus assorted applications and tools.
i-net Clear Reports (formerly i-net Crystal-Clear) is a very powerful reporting solution. It can accommodate a broad range of reporting needs, from a simple standalone application to a really big enterprise Web solution. It can produce many different output formats like Java Viewer, PDF, HTML, PS, RTF, XLS, TXT, CSV, SVG, and XML. It can generate reports from many different data sources like JDBC, ODBC, Java API, JNDI Data Source, and without data.
System# is a .NET library intended for the description of real-time embedded systems. It comes with a built-in simulator kernel and a code transformation engine that converts a design into synthesizable VHDL. The main focus is currently the development of FPGA designs. System# not only supports register-transfer-level (RTL) descriptions whose translation to VHDL is straightforward, but is also capable of converting clocked threads with wait statements to a synthesizable VHDL state machine. Furthermore, System# introduces synthesizable transaction-level modeling features. From a technological point of view, it uses reflection and assembly code (CIL) decompilation to reconstruct an abstract syntax tree (AST) from the system design. The AST conforms to SysDOM, a document object model for describing component-based reactive systems. An unparsing stage converts the AST to VHDL. The decompilation process can be instrumented in various ways by attribute-based programming. Furthermore, transformations of the AST itself are possible. This enables implementation of advanced features such as converting clocked threads to finite state machines.