127 projects tagged "Electronic Design Automation (EDA)"

Download Website Updated 31 Jan 2002 SpiceViewMG

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Pop 19.70
Vit 67.09

SpiceViewMG consists of two main parts. It is aimed at NG-spice users. The first is a spice language viewer which picks out different elements of the spice, such as transistors or models, thus making editing easier. The second component is an interactive spice plotter.

Download Website Updated 13 Aug 2005 THUD

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Pop 17.06
Vit 4.65

THUD is a register transfer level (RTL) simulation environment optimized for cycle- based designs. The design is expressed in TH, a Scheme-based hardware description language (HDL) that supports 1/0/x operators and hierarchical instantiation. THUD can be used as a library, in batch mode, or through one of its interactive interfaces.

Download Website Updated 27 Jan 2014 TTA-based Co-design Environment

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Pop 108.87
Vit 11.81

TTA-based Co-design Environment (TCE) is a toolset that provides a complete co-design flow from C programs down to synthesizable VHDL and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network.

Download Website Updated 13 May 2003 Taverna

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Pop 48.79
Vit 1.00

Taverna is a collection of workflow enactment and description components, including a high level language for workflows called Scufl (Simple Conceptual Unified Flow Language), a pure Java object model, parser to populate the model, and a set of views and controllers (including some Swing components to drop into your workflow-enabled applications). In order to actually run workflows you also need the myGrid workflow enactment engine.

No download Website Updated 16 Mar 2007 The CBOLD Framework

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Pop 14.59
Vit 51.29

The CBOLD framework is a set of C++ classes and related source code for capturing board-level electronic designs. It allows the designer to capture and process an electronic board-level design using a text editor (or IDE) and a C++ compiler. It provides a concise, intuitive notation for schematicless capture of board-level designs. Instead of entering a schematic into an EDA tool, the designer creates a C++ program that describes the design and the desired outputs. When the program is compiled and run, it verifies the legality of the design and writes output files (CAD layout netlist, bill of materials, FPGA constraint files, etc.) to disk. Code primarily consists of definitions of modules, which are analogous to pages of a schematic design.

Download Website Updated 10 Sep 2004 The PEP tool

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Pop 37.35
Vit 1.47

PEP is a modeling and verification framework for parallel systems. It provides a large number of different modelling languages (e.g. SDL, B(PN)^2, Petri nets, Process algebras and Finite Automata), and verification techniques (e.g. reachability and temporal logic model checking). Due to its Tcl/Tk-based GUI, PEP is easily extensible to other analysis or specification tools. The framework offers fully integrated simulation and debugging features on all levels.

Download Website Updated 15 Jul 2002 Transcalc

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Pop 26.68
Vit 1.81

Transcalc is an analysis and synthesis tool for calculating the electrical and physical properties of different kinds of RF and microwave transmission lines. It uses GTK+ for its user interface. For each type of transmission line, it presents you with dialog boxes which allow you to enter values for the various parameters, and either calculate its electrical properties (analyze) or use the given electrical requirements to sythesize physical parameters of the required transmission line.

Download Website Updated 18 Apr 2009 UrJTAG

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Pop 46.82
Vit 2.24

UrJTAG aims to create an enhanced, modern tool for communicating over JTAG with flash chips, CPUs, and many more. It takes on the well proven openwince jtag tools code. Future plans include conversion of the code base into a library that can be used with other applications. A flexible remote communication protocol that can be used over almost any type of serial link (including TCP/IP) is currently being defined.

No download Website Updated 18 Apr 2003 Verilator

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Pop 34.76
Vit 63.71

Verilator is a cycle based synthesizable Verilog hardware design language compiler. It produces C++ or SystemC output with speeds compariable to commercial products.

No download Website Updated 02 Oct 2003 ViPEC

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Pop 43.37
Vit 6.35

VIPEC is an network analyser for electrical networks. It takes a description of an electrical network, and performs a simulation of the circuit response in the frequency domain. Output is in the form of 2-port parameters, and can be plotted on a grid and in Smithchart format. VIPEC supports various lumped circuit elements, as well as elements like transmission lines and 2-port data files.

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bb_log

A fast and tiny logger for Java.

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CorneliOS

A virtual Web OS.