Resistors is a program to calculate the most suitable E-series resistors for voltage dividers or for generating other values by putting two resistors in parallel. It is especially useful for selecting resistor values for the voltage dividers used in variable voltage regulators. In effect, the voltage in the middle of the divider is known, and you want to achieve a regulated voltage (the top value).
Salut is a small program that performs calculations on simple networks around two-port devices (like transistors) characterized by s-parameters, at radio frequencies (RF). It has the ability to model components in series with a two-port block, like an inductance from the common lead to ground. Salut is also not restricted to the usual common emitter or common source configuration even though many semiconductor manufacturers only provide s-parameters for this case.
Scheture is a hierarchical schematic capture system with built-in netlisters for Spice and Verilog. It has built-in plotting for Postscript, HP PCL and HP GL/2 printers and plotters. It includes a set of symbol primitives, and allows user-defined symbol primitives to allow for extensive customization of primitive properties. The system supports wire buses and iterated instances. The system also supports global pins and implicitly connected pins on a specific sheet. Supported platforms include Solaris and Linux (32- and 64-bit).
Signal Generator is a laboratory noise/sound generator which can be used to generate accurate sounds in fixed frequency, 2-channels (two frequencies going at once), a sweep-pattern, or in a specified sequence. It is useful when you need to generate a fixed sound for whatever purpose (in the laboratory, for sound effects, etc)
Signs is a development environment for hardware designs in various hardware description languages. The tackled tasks are compilation, synthesis, simulation, and testing of designs. Due to the integration of these main areas, it provides the ability to debug designs in an all-embracing manner by switching between source code, netlist, and simulation. Supported languages include VHDL and the ISCAS benchmark format. Signs comes in two flavors: a command-line only version useful for processing and analyzing large netlists and as an Eclipse plugin for hardware design and simulation.
Slam is a mature IC Layout editor with the ability to edit very large designs (such as stream files larger than 10GB). Novel features include threading for redraw, support for displaying on multiple X servers simultaneously, and a Tcl interface to the database for user extensibility. The system is a library based system with multi-user support. Programmable structures (P-Cells) are available in Tcl. The editor includes gds input and output.
SoC GDS is a platform for enabling hierarchical SoC integration and verification across traditional EDA frameworks based on Virtual Components per the VSIA guidelines. It is also a fast viewer and processor for native GDSII files. It encompasses a set of powerful functions allowing automatic cell renaming, grid verifications, GDS II files merging (AND), physical comparison (XOR), hierarchy modifications, and conversion to text format.
Spice+ is a general-purpose circuit simulation program based directly on Spice3f5. Its main purpose is to allow university students and other interested people to simulate their circuits without buying expensive simulation programs or being limited by free trial versions of such software. Since source code is available, students or researchers can use it as a basis for new models and algorithms.