The CBOLD framework is a set of C++ classes and related source code for capturing board-level electronic designs. It allows the designer to capture and process an electronic board-level design using a text editor (or IDE) and a C++ compiler. It provides a concise, intuitive notation for schematicless capture of board-level designs. Instead of entering a schematic into an EDA tool, the designer creates a C++ program that describes the design and the desired outputs. When the program is compiled and run, it verifies the legality of the design and writes output files (CAD layout netlist, bill of materials, FPGA constraint files, etc.) to disk. Code primarily consists of definitions of modules, which are analogous to pages of a schematic design.
SoC GDS is a platform for enabling hierarchical SoC integration and verification across traditional EDA frameworks based on Virtual Components per the VSIA guidelines. It is also a fast viewer and processor for native GDSII files. It encompasses a set of powerful functions allowing automatic cell renaming, grid verifications, GDS II files merging (AND), physical comparison (XOR), hierarchy modifications, and conversion to text format.
YaPIDE aims to be a fully featured Microchip PIC simulator for Linux (and probably other Unixes). It is a GUI that provides a viewer for RAM, ROM, stack, breakpoints, and watchpoints, and has a source editor with inline debugging (ASM). The chip currently supported is the 16F628 (partial).
Signs is a development environment for hardware designs in various hardware description languages. The tackled tasks are compilation, synthesis, simulation, and testing of designs. Due to the integration of these main areas, it provides the ability to debug designs in an all-embracing manner by switching between source code, netlist, and simulation. Supported languages include VHDL and the ISCAS benchmark format. Signs comes in two flavors: a command-line only version useful for processing and analyzing large netlists and as an Eclipse plugin for hardware design and simulation.
Pyspice is an easily extendable SPICE pre-processor written in Python to reduce simulation times with little loss in accuracy. It was inspired by John Sheahan's spicepp and developed as a modular and extensible method of pre-processing netlists. Primarily, it has been used to reduce netlists from the output of layout extraction tools. It combines parallel MOSFETs and capacitors, and optionally drops small capacitors. Planned improvements include a hierarchical namespace (e.g. .subckt/.ends and .alter blocks), more devices, and .include/.model support. Unlike other pre-processors, comments and blank lines are preserved in their relative positions. This keeps the output netlist readable for subsequent editing or processing.
ibistools is a small set of command-line tools that aid a PCB designer working with IBIS models. It currently consists of a full IBIS v4.1 parser and an IBIS to SPICE translator. IBIS (I/O Buffer Information Specification) is a standard, human-readable, machine-readable format for publishing IC specifications.
PySTDF is a Python module which makes it easy to work with STDF (Teradyne's Standard Test Data Format). STDF is a commonly-used file format in semiconductor tests. Automated test equipment (ATE) from such vendors as Teradyne, Verigy, LTX, Credence, and others supports this format. PySTDF provides event-based stream parsing of STDF version 4, indexers that help structure the data into a more useful tabular form, and the ability to generate missing summary records or new types of derivative records. The parser architecture is very flexible and can easily be extended to support STDF version 3 and custom record types.