127 projects tagged "Electronic Design Automation (EDA)"

No download Website Updated 02 Oct 2003 ViPEC

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Pop 43.37
Vit 6.35

VIPEC is an network analyser for electrical networks. It takes a description of an electrical network, and performs a simulation of the circuit response in the frequency domain. Output is in the form of 2-port parameters, and can be plotted on a grid and in Smithchart format. VIPEC supports various lumped circuit elements, as well as elements like transmission lines and 2-port data files.

No download Website Updated 08 Jul 2003 GraphPak for Qt

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Pop 42.19
Vit 1.00

GraphPak is a programming library of 2D and 3D charting objects for the Qt toolkit. It provides software developers with a set of C++ objects to easily create charts or graphs that aid in the visual presentation of technical and business data. This release includes Bar, Line, Pie, Ring, Area, Hi-Lo, Box and Whisker, and Polar charts. It is based on the KD Chart product from Klarälvdalens Datakonsult AB.

Download Website Updated 28 Aug 2003 JHDL

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Pop 41.58
Vit 2.62

JHDL is a set of FPGA CAD tools which allows the user to design the structure and layout of a circuit, debug the circuit in simulation, netlist, and interface with backend tools for synthesis, etc. It is an exploratory attempt to identify the key features and functionality of good FPGA tools.

Download Website Updated 07 Feb 2003 XML PCB Render

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Pop 41.57
Vit 1.00

The XML PCB Renderer takes an XML definition of a printed circuit board (consisting of pads, tracks and components) and renders it to a PNG file suitable for printing onto paper or transparency ready for UV exposure.

No download Website Updated 30 Jan 2001 BitGen

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Pop 41.33
Vit 2.04

BitGen accepts text strings of 1's, 0's and hex digits and converts them to equivalent "pwl" voltage sources for inclusion in netlists for circuit simulation (with SPICE or Spectre, for example). Periodic waveforms (eg, clocks) can be exported as "pulse" voltage sources. Parameters such as rise time, fall time, pulse width and duty cycle can be set on a waveform-by-waveform basis. BitGen is written in Perl with the Perl/Tk toolkit and has an easy-to-use graphical interface.

Download Website Updated 28 Feb 2001 FreeSCADA toolbox

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Pop 39.29
Vit 69.55

The FreeSCADA project develops a set of libs to help implement a simple control/acquisition system quickly and efficiently.

Download Website Updated 26 Apr 2005 pdnmesh

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Pop 38.34
Vit 3.35

pdnmesh is an automatic, 2D Delaunay mesh generator, and a solver for finite element analysis. It is capable of producing PostScript output of the mesh and contours. It is possible to use DXF files as input after filtering. It requires GTK/GtkGLExt and Mesa/OpenGL or MFC (Win32), and is written in C.

Download Website Updated 10 Sep 2004 The PEP tool

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Pop 37.35
Vit 1.47

PEP is a modeling and verification framework for parallel systems. It provides a large number of different modelling languages (e.g. SDL, B(PN)^2, Petri nets, Process algebras and Finite Automata), and verification techniques (e.g. reachability and temporal logic model checking). Due to its Tcl/Tk-based GUI, PEP is easily extensible to other analysis or specification tools. The framework offers fully integrated simulation and debugging features on all levels.

No download Website Updated 30 Jan 2001 Dinotrace

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Pop 37.28
Vit 1.00

Dinotrace is a graphical viewer for Signal Wave files. It supports the output from Verilog, VCS, and other simulators in addition to simple ASCII. It includes a mode for GNU Emacs allowing signal values to be backannotated into Verilog or C source code.

Download Website Updated 28 Jul 2005 QCADesigner

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Pop 37.09
Vit 2.07

QCADesigner is a Quantum-Dot Cellular Automata (QCA) circuit simulator. With powerful CAD capabilities, it allows the designer to quickly layout and simulate QCA circuits constructed with thousands of QCA cells. QCA is one of several emerging nanotechnologies with potential applications in future computers.

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Project Spotlight

bb_log

A fast and tiny logger for Java.

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CorneliOS

A virtual Web OS.