ChipVault is a chip development program for organizing VHDL and Verilog designs. ChipVault displays designs hierarchically and provides for rapid design navigation and editor launching. ChipVault provides hooks for performing bottom-up tasks such as launching RTL compilers, synthesis, block generation and instantiation, and includes simple to use Revision Control and Issue Tracking systems to help facilitate large group design projects with multiple designers and hundreds of design files. ChipVault is written in Perl and is small, fast, and efficient.
Confluence is a functional programming language for reactive system design, including FPGAs, ASICs, and hard-real-time software. Confluence system descriptions have a large information to linecount ratio. It is typically two to five times more compact than Verilog. Confluence can compile a single body of source code into to Verilog, VHDL, C, and NuSMV.
Bartels AutoEngineer is a commercial CAD tool for electrical / computer engineers. It supports Linux, Win95/NT, DOS, OS/2, HP, DEC and Sun. Features include a schematic Editor with hierarchical design support, Forward/Backward Annotation, PCB Layout system, CAM Processor, CAM View, Integrated, object-oriented database system, User Language Compiler, utility programs for database management, foreign net list and design data import, etc. and part libraries for SCM and PCB layout
Taverna is a collection of workflow enactment and description components, including a high level language for workflows called Scufl (Simple Conceptual Unified Flow Language), a pure Java object model, parser to populate the model, and a set of views and controllers (including some Swing components to drop into your workflow-enabled applications). In order to actually run workflows you also need the myGrid workflow enactment engine.
Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT/FST dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.
DiaCanvas is a generalized version of the drawing canvas used by DIA. It extends some features used by DIA and adds new ones, while preserving as many of the original features as possible. This project is no longer actively maintained. It is suggested that you try DiaCanvas2 instead.
UrJTAG aims to create an enhanced, modern tool for communicating over JTAG with flash chips, CPUs, and many more. It takes on the well proven openwince jtag tools code. Future plans include conversion of the code base into a library that can be used with other applications. A flexible remote communication protocol that can be used over almost any type of serial link (including TCP/IP) is currently being defined.
JCCad is a project to develop a 2D/3D CAD program that can be used to create technical drawings. One of the main goals of this project is to include a plugin system to allow usuaries to make new commands. In this way it will be easy to use the program for any particular task. JCCad provides an easy interface with a command line.
Liquid PCB is a computer aided design application for designing printed circuit boards. Unlike other PCB CAD applications, you are not restricted to straight tracks and 45º angles. Instead, you can freely draw tracks any way you like, and the tracks themselves will move and bend as required to maintain your design rules. Vias and components are also free to move and rotate. The user interface exposes all functions through the multi-directional expanding mouse menu and the keyboard instead of through icons and menus.