DOLPHIN SLED is a hierarchical schematic entry solution with graphic linking of components, hierarchical configuration of the netlist, and multi-language netlisting (SPICE, Verilog, VHDL-AMS, etc.). Interoperability with other schematic entry tools, particularly the ECS family (including Synario, Cohesion, and Laker-AMS) is ensured for capitalizing on legacy designs and cooperative work. Interoperability is ensured through standard design exchange formats (EDIF2) and scriptability for customization.
Balsa is an asynchronous circuit simulation and synthesis system. Balsa is built around the Handshake Circuits methology, and it can generate gate level netlists from high-level descriptions in the Balsa language. Both dual-rail (QDI) and single-rail (bundled data) circuits can be generated.
Electronic Design Automation - Index is a system that can be used in the electronic world to keep track of your: Schematic, Printed Circuit Board, Front Plate, and Programmable Logic Unit numbers. This is very useful when you have drawn many electronic schematics and PCBs in an EDA program such as Eagle, gEDA, Protel, or Orcad. It's also useful if you've created a front plate layout in an image editor such as GIMP, Corel Draw, or Photoshop.
Confluence is a functional programming language for reactive system design, including FPGAs, ASICs, and hard-real-time software. Confluence system descriptions have a large information to linecount ratio. It is typically two to five times more compact than Verilog. Confluence can compile a single body of source code into to Verilog, VHDL, C, and NuSMV.
FSMDesigner is a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. It uses the Simple-Moore FSM model, guaranteeing efficient fast complex control circuits. It features graphical design of FSMs, support for automatic default transitions, validation of FSMs, a well-defined XML file format, generation of RTL HDL output for both Verilog and VHDL, full scriptability in Python, a modern GUI with undo and redo, simulation mode support, and table based data manipulation.
ChipVault is a chip development program for organizing VHDL and Verilog designs. ChipVault displays designs hierarchically and provides for rapid design navigation and editor launching. ChipVault provides hooks for performing bottom-up tasks such as launching RTL compilers, synthesis, block generation and instantiation, and includes simple to use Revision Control and Issue Tracking systems to help facilitate large group design projects with multiple designers and hundreds of design files. ChipVault is written in Perl and is small, fast, and efficient.
HDLmaker generates hierarchical Verilog and VHDL code, PCB netlists, simulation and synthesis scripts/projects/make files, and schematics. It can translate Verilog/VHDL and HDLmaker projects into HTML, including extensive hyperlinking between the modules. It can also translate PADS PCB netlists into Verilog and VHDL and can do some simple VHDL to Verilog translations. HDLMaker synplifies the development of complex FPGAs and ASICs, and has extensive support for most Xilinx FPGAs.