Signs is a development environment for hardware designs in various hardware description languages. The tackled tasks are compilation, synthesis, simulation, and testing of designs. Due to the integration of these main areas, it provides the ability to debug designs in an all-embracing manner by switching between source code, netlist, and simulation. Supported languages include VHDL and the ISCAS benchmark format. Signs comes in two flavors: a command-line only version useful for processing and analyzing large netlists and as an Eclipse plugin for hardware design and simulation.
Balsa is an asynchronous circuit simulation and synthesis system. Balsa is built around the Handshake Circuits methology, and it can generate gate level netlists from high-level descriptions in the Balsa language. Both dual-rail (QDI) and single-rail (bundled data) circuits can be generated.
SoC GDS is a platform for enabling hierarchical SoC integration and verification across traditional EDA frameworks based on Virtual Components per the VSIA guidelines. It is also a fast viewer and processor for native GDSII files. It encompasses a set of powerful functions allowing automatic cell renaming, grid verifications, GDS II files merging (AND), physical comparison (XOR), hierarchy modifications, and conversion to text format.
Electronic Design Automation - Index is a system that can be used in the electronic world to keep track of your: Schematic, Printed Circuit Board, Front Plate, and Programmable Logic Unit numbers. This is very useful when you have drawn many electronic schematics and PCBs in an EDA program such as Eagle, gEDA, Protel, or Orcad. It's also useful if you've created a front plate layout in an image editor such as GIMP, Corel Draw, or Photoshop.
iBookshelf is an application for cataloging your book collection and designing bookshelves based on this data. It supports ISBN entry using a CueCat, a standard barcode scanner, or manual entry. Book data is automatically fetched from Amazon Web services. Manual book entry is possible for non-catalogued books. Bookshelf design is done graphically with the Cairo drawing library, and is based on the most efficient book order.
FSMDesigner is a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. It uses the Simple-Moore FSM model, guaranteeing efficient fast complex control circuits. It features graphical design of FSMs, support for automatic default transitions, validation of FSMs, a well-defined XML file format, generation of RTL HDL output for both Verilog and VHDL, full scriptability in Python, a modern GUI with undo and redo, simulation mode support, and table based data manipulation.
HDLmaker generates hierarchical Verilog and VHDL code, PCB netlists, simulation and synthesis scripts/projects/make files, and schematics. It can translate Verilog/VHDL and HDLmaker projects into HTML, including extensive hyperlinking between the modules. It can also translate PADS PCB netlists into Verilog and VHDL and can do some simple VHDL to Verilog translations. HDLMaker synplifies the development of complex FPGAs and ASICs, and has extensive support for most Xilinx FPGAs.