HDLmaker generates hierarchical Verilog and VHDL code, PCB netlists, simulation and synthesis scripts/projects/make files, and schematics. It can translate Verilog/VHDL and HDLmaker projects into HTML, including extensive hyperlinking between the modules. It can also translate PADS PCB netlists into Verilog and VHDL and can do some simple VHDL to Verilog translations. HDLMaker synplifies the development of complex FPGAs and ASICs, and has extensive support for most Xilinx FPGAs.
Ngspice is a mixed-level/mixed-signal circuit simulator based on three open source software packages: Spice3f5, Cider1b1, and Xspice. Spice3 is the most famous and widely used circuit simulator. Cider is mixed-level simulator that includes Spice3f5 and adds DSIM, a device simulator. Cider couples the circuit level simulator to the device simulator to provide greater simulation accuracy (at the expense of greater simulation time). Xspice is an extension to Spice3 that provides code modeling support and simulation of digital components through an embedded event driven algorithm.
SoC GDS is a platform for enabling hierarchical SoC integration and verification across traditional EDA frameworks based on Virtual Components per the VSIA guidelines. It is also a fast viewer and processor for native GDSII files. It encompasses a set of powerful functions allowing automatic cell renaming, grid verifications, GDS II files merging (AND), physical comparison (XOR), hierarchy modifications, and conversion to text format.