JHDL is a set of FPGA CAD tools which allows the user to design the structure and layout of a circuit, debug the circuit in simulation, netlist, and interface with backend tools for synthesis, etc. It is an exploratory attempt to identify the key features and functionality of good FPGA tools.
Platform Independent Petri Net Editor (PIPE) creates and analyses Petri Nets quickly, efficiently, and effectively. A key design feature is the modular approach adopted for analysis, enabling new modules to be written easily and powerfully, using built-in data layer methods for standard calculations. Six analysis modules are provided, including Invariant Analysis, State-Space Analysis (deadlock, etc.), and Simulation Analysis and Classification. PIPE adheres to the XML Petri net standard (PNML). The file format for saving and loading Petri Nets is extensible through the use of XSLT, the default being PNML.
Taverna is a collection of workflow enactment and description components, including a high level language for workflows called Scufl (Simple Conceptual Unified Flow Language), a pure Java object model, parser to populate the model, and a set of views and controllers (including some Swing components to drop into your workflow-enabled applications). In order to actually run workflows you also need the myGrid workflow enactment engine.
PEP is a modeling and verification framework for parallel systems. It provides a large number of different modelling languages (e.g. SDL, B(PN)^2, Petri nets, Process algebras and Finite Automata), and verification techniques (e.g. reachability and temporal logic model checking). Due to its Tcl/Tk-based GUI, PEP is easily extensible to other analysis or specification tools. The framework offers fully integrated simulation and debugging features on all levels.
Signs is a development environment for hardware designs in various hardware description languages. The tackled tasks are compilation, synthesis, simulation, and testing of designs. Due to the integration of these main areas, it provides the ability to debug designs in an all-embracing manner by switching between source code, netlist, and simulation. Supported languages include VHDL and the ISCAS benchmark format. Signs comes in two flavors: a command-line only version useful for processing and analyzing large netlists and as an Eclipse plugin for hardware design and simulation.
FerFT is a multi-purpose spectral analyzer based on the successive Fourier transformation method. It features an input signal monitor which can sample input signals through a microphone with various sample rates and show them graphically on the panel. It also lets you calculate power spectra successively along with sampled input signals and show them graphically on the panel. Finally, it provides a filter to modify spectra and regenerate signals from them.
JSDAI is a toolkit around STEP or ISO 10303, the STandard for the Exchange of Product model data. It supports the Express data modelling language as defined in ISO 10303-11 and provides data exchange capabilities according to ISO 10303-21 STEP-file and ISO 10303-28 STEP-XML. JSDAI Runtime is an API according ISO 10303-22, the Standard Data Access Interface (SDAI) for the Java programming language, ISO 10303-27. JSDAI Developer is for the development of Express data models, including Express-G diagrams.