LayoutEditor is an IC/MEMS layout editor. It features all angle elements, a font generator, macros, Boolean operations, drc, netlist-driven layout, LVS, and cross-platform compatibility. Supported formats include Calma GDSII, OASIS (Open Artwork System Interchange Standard), DXF, CIF (Caltech Intermediate Form), Gerber, DEF/LEF, and many others.
Scheture is a hierarchical schematic capture system with built-in netlisters for Spice and Verilog. It has built-in plotting for Postscript, HP PCL and HP GL/2 printers and plotters. It includes a set of symbol primitives, and allows user-defined symbol primitives to allow for extensive customization of primitive properties. The system supports wire buses and iterated instances. The system also supports global pins and implicitly connected pins on a specific sheet. Supported platforms include Solaris and Linux (32- and 64-bit).
JTAGTest is an IEEE 1149.1 JTAG Boundary scan tester for embedded designers, production houses, and service companies. It provides a significant aid for PCB debugging, prototyping, testing, and repairing. Using an IEEE 1149.1 (JTAG) boundary-scan, the device pin signals or internal signals can be monitored in real-time without interfering with normal device operation, and you can change pin state manually. It runs under Wine on 32-bit Linux distributions using special Linux support libraries, which are included in the distribution.
Bartels AutoEngineer is a commercial CAD tool for electrical / computer engineers. It supports Linux, Win95/NT, DOS, OS/2, HP, DEC and Sun. Features include a schematic Editor with hierarchical design support, Forward/Backward Annotation, PCB Layout system, CAM Processor, CAM View, Integrated, object-oriented database system, User Language Compiler, utility programs for database management, foreign net list and design data import, etc. and part libraries for SCM and PCB layout