57 projects tagged "Electronic Design Automation (EDA)"
Updated 22 Apr 2013
Slam-Edit
| Pop | 148.59 |
|---|---|
| Vit | 46.87 |
Slam is a mature IC Layout editor with the ability to edit very large designs (such as stream files larger than 10GB). Novel features include threading for redraw, support for displaying on multiple X servers simultaneously, and a Tcl interface to the database for user extensibility. The system is a library based system with multi-user support. Programmable structures (P-Cells) are available in Tcl. The editor includes gds input and output.
Updated 21 Jan 2013
TTA-based Co-design Environment
| Pop | 105.13 |
|---|---|
| Vit | 9.53 |
TTA-based Co-design Environment (TCE) is a toolset that provides a complete co-design flow from C programs down to synthesizable VHDL and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network.
Updated 16 Jul 2012
DOLPHIN SLED
| Pop | 85.50 |
|---|---|
| Vit | 9.08 |
DOLPHIN SLED is a hierarchical schematic entry solution with graphic linking of components, hierarchical configuration of the netlist, and multi-language netlisting (SPICE, Verilog, VHDL-AMS, etc.). Interoperability with other schematic entry tools, particularly the ECS family (including Synario, Cohesion, and Laker-AMS) is ensured for capitalizing on legacy designs and cooperative work. Interoperability is ensured through standard design exchange formats (EDIF2) and scriptability for customization.
Updated 18 May 2012
Scheture
| Pop | 72.75 |
|---|---|
| Vit | 7.51 |
Scheture is a hierarchical schematic capture system with built-in netlisters for Spice and Verilog. It has built-in plotting for Postscript, HP PCL and HP GL/2 printers and plotters. It includes a set of symbol primitives, and allows user-defined symbol primitives to allow for extensive customization of primitive properties. The system supports wire buses and iterated instances. The system also supports global pins and implicitly connected pins on a specific sheet. Supported platforms include Solaris and Linux (32- and 64-bit).
Updated 28 Feb 2012
ASCO
| Pop | 58.17 |
|---|---|
| Vit | 9.31 |
The ASCO project aims to bring circuit optimization capabilities to existing SPICE simulators using a high-performance parallel differential evolution (DE) optimization algorithm. It supports Eldo, HSPICE, LTSpice, Spectre, and Qucs.
Updated 05 Aug 2011
ReliaFree
| Pop | 20.25 |
|---|---|
| Vit | 1.85 |
The ReliaFree Project is an alternative to commercial, proprietary reliability, availability, maintainability, and safety (RAMS) analysis software. The ReliaFree Project is an integrated suite of tools. Any number of analyses can be linked together such that an update to one module will result in all linked modules being updated appropriately. This approach provides a closed loop life-cycle with visibility into a product's performance throughout. The same database is used to store field failure data as is used to store design prediction information.
Updated 29 May 2011
mprfgen
| Pop | 18.28 |
|---|---|
| Vit | 26.83 |
mprfgen is a multi-port memory generator that can be used for VHDL designs. It can generate either generic or Xilinx-specific (through component instantiation) multi-port memories.
Updated 15 May 2011
Easy Funktion
| Pop | 96.12 |
|---|---|
| Vit | 10.89 |
Easy Funktion is 2D function plotter software with an equation solver. It has an office-like GUI frontend and features a built-in pocket calculator, calculating with complex numbers (with special extensions for electronics, e.g. capacitor/inductor impedance), a function to export to spreadsheet software, and an advanced formula editor with automatic formatting.
Updated 11 Apr 2011
ACL2
| Pop | 88.45 |
|---|---|
| Vit | 5.65 |
ACL2 is a mathematical logic, programming language, and mechanical theorem prover based on the applicative subset of Common Lisp. It is an "industrial-strength" version of the NQTHM or Boyer/Moore theorem prover, and has been used for the formal verification of commercial microprocessors, the Java Virtual Machine, interesting algorithms, and so forth.
Updated 04 Apr 2011
LayoutEditor
| Pop | 77.25 |
|---|---|
| Vit | 8.17 |
LayoutEditor is an IC/MEMS layout editor. It features all angle elements, a font generator, macros, Boolean operations, drc, netlist-driven layout, LVS, and cross-platform compatibility. Supported formats include Calma GDSII, OASIS (Open Artwork System Interchange Standard), DXF, CIF (Caltech Intermediate Form), Gerber, DEF/LEF, and many others.
