RSS 2 projects tagged "Electronic Design Automation (EDA)"

No download Website Updated 17 Feb 2005 Confluence System Design Language

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Pop 57.83
Vit 1.75

Confluence is a functional programming language for reactive system design, including FPGAs, ASICs, and hard-real-time software. Confluence system descriptions have a large information to linecount ratio. It is typically two to five times more compact than Verilog. Confluence can compile a single body of source code into to Verilog, VHDL, C, and NuSMV.

No download Website Updated 09 Dec 2004 InFormal

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Pop 30.46
Vit 1.00

InFormal provides formal verification of digital hardware. Built on the FNF open netlist standard, it creates a link between Icarus Verilog, the leading open source Verilog implementation, and NuSMV, the leading open soure model checker.

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Sensor Readout

Sensor readout for Android devices.

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Open Tax Solver

Tax preparation software for use in the USA.