10 projects tagged "Electronic Design Automation (EDA)"

Pop	150.64
Vit	42.18

Slam is a mature IC Layout editor with the ability to edit very large designs (such as stream files larger than 10GB). Novel features include threading for redraw, support for displaying on multiple X servers simultaneously, and a Tcl interface to the database for user extensibility. The system is a library based system with multi-user support. Programmable structures (P-Cells) are available in Tcl. The editor includes gds input and output.

Pop	72.19
Vit	7.45

Scheture is a hierarchical schematic capture system with built-in netlisters for Spice and Verilog. It has built-in plotting for Postscript, HP PCL and HP GL/2 printers and plotters. It includes a set of symbol primitives, and allows user-defined symbol primitives to allow for extensive customization of primitive properties. The system supports wire buses and iterated instances. The system also supports global pins and implicitly connected pins on a specific sheet. Supported platforms include Solaris and Linux (32- and 64-bit).

Pop	62.53
Vit	8.48

Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT/FST dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.

Pop	20.00
Vit	1.00

The QConsole class is a custom widget that implements a basic console, written in C++ and relying on Qt. It implements several features and is intended to be inherited from in order to have a "real" console for a specific scripting language, shell, etc. Example implementations for TCL and Python are included.

Pop	35.20
Vit	1.42

MMTL (Multilayer Multiconductor Transmission Line) is a 2-D and 2.5-D electromagnetic modeling tool suite. It generates transmission parameters and SPICE models from descriptions of electronics interconnect dimensions and materials properties.

Pop	44.27
Vit	1.48

PEP is a modeling and verification framework for parallel systems. It provides a large number of different modelling languages (e.g. SDL, B(PN)^2, Petri nets, Process algebras and Finite Automata), and verification techniques (e.g. reachability and temporal logic model checking). Due to its Tcl/Tk-based GUI, PEP is easily extensible to other analysis or specification tools. The framework offers fully integrated simulation and debugging features on all levels.

Pop	20.20
Vit	1.00

SpiceWish is a spice plotter. Features include Trace Place, allowing the easy grouping and comparison of traces against each other, and an editor which allows the re-running of simulations to plot old traces against new for easy comparison.

Pop	22.72
Vit	64.27

SpiceViewMG consists of two main parts. It is aimed at NG-spice users. The first is a spice language viewer which picks out different elements of the spice, such as transistors or models, thus making editing easier. The second component is an interactive spice plotter.

Pop	20.86
Vit	2.65

Spgmr08 is a Linux software package for programming Motorola MC68HC908 microcontrollers. It has a command line tool, an interactive mode, and a Tcl/Tk GUI interface. It currently supports the GP32 and AB32 processors.

Pop	50.20
Vit	66.84

The FreeSCADA project develops a set of libs to help implement a simple control/acquisition system quickly and efficiently.