RSS 95 projects tagged "Electronic Design Automation (EDA)"

No download Website Updated 10 Jan 2014 Slam-Edit

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Pop 140.45
Vit 26.99

Slam is a mature IC Layout editor with the ability to edit very large designs (such as stream files larger than 10GB). Novel features include threading for redraw, support for displaying on multiple X servers simultaneously, and a Tcl interface to the database for user extensibility. The system is a library based system with multi-user support. Programmable structures (P-Cells) are available in Tcl. The editor includes gds input and output.

Download Website Updated 22 Jul 2013 ASCO

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Pop 78.00
Vit 13.07

The ASCO project aims to bring circuit optimization capabilities to existing SPICE simulators using a high-performance parallel differential evolution (DE) optimization algorithm. It supports Eldo, HSPICE, LTSpice, Spectre, Qucs, and ngspice.

No download Website Updated 22 Jun 2013 Electric

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Pop 174.79
Vit 18.69

Electric is a complete EDA system that can handle many forms of circuit design, including Schematic Capture (digital and analog), Custom IC layout, Logic Simulation, Electro-mechanical hybrid layout, Programmable logic (FPGAs) and much more.

No download Website Updated 01 Nov 2012 GTKWave

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Pop 146.54
Vit 26.28

GTKWave is a wave viewer for Verilog simulation. The viewer supports execution of Tcl scripts and enhanced Drag and Drop operations.

Download Website Updated 16 Jul 2012 DOLPHIN SLED

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Pop 61.48
Vit 6.83

DOLPHIN SLED is a hierarchical schematic entry solution with graphic linking of components, hierarchical configuration of the netlist, and multi-language netlisting (SPICE, Verilog, VHDL-AMS, etc.). Interoperability with other schematic entry tools, particularly the ECS family (including Synario, Cohesion, and Laker-AMS) is ensured for capitalizing on legacy designs and cooperative work. Interoperability is ensured through standard design exchange formats (EDIF2) and scriptability for customization.

No download Website Updated 18 May 2012 Scheture

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Pop 65.73
Vit 5.80

Scheture is a hierarchical schematic capture system with built-in netlisters for Spice and Verilog. It has built-in plotting for Postscript, HP PCL and HP GL/2 printers and plotters. It includes a set of symbol primitives, and allows user-defined symbol primitives to allow for extensive customization of primitive properties. The system supports wire buses and iterated instances. The system also supports global pins and implicitly connected pins on a specific sheet. Supported platforms include Solaris and Linux (32- and 64-bit).

Download Website Updated 08 Aug 2011 BeRTOS

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Pop 101.98
Vit 5.20

BeRTOS is a real time operating system (RTOS) suitable for embedded platforms. It runs on many microprocessors and microcontrollers, ranging from 8-bit to 32-bit CPUs and even PCs.

No download Website Updated 05 Aug 2011 ReliaFree

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Pop 16.79
Vit 1.61

The ReliaFree Project is an alternative to commercial, proprietary reliability, availability, maintainability, and safety (RAMS) analysis software. The ReliaFree Project is an integrated suite of tools. Any number of analyses can be linked together such that an update to one module will result in all linked modules being updated appropriately. This approach provides a closed loop life-cycle with visibility into a product's performance throughout. The same database is used to store field failure data as is used to store design prediction information.

Download Website Updated 10 Jun 2011 Platform Independent Petri Net Editor

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Pop 72.68
Vit 5.91

Platform Independent Petri Net Editor (PIPE) creates and analyses Petri Nets quickly, efficiently, and effectively. A key design feature is the modular approach adopted for analysis, enabling new modules to be written easily and powerfully, using built-in data layer methods for standard calculations. Six analysis modules are provided, including Invariant Analysis, State-Space Analysis (deadlock, etc.), and Simulation Analysis and Classification. PIPE adheres to the XML Petri net standard (PNML). The file format for saving and loading Petri Nets is extensible through the use of XSLT, the default being PNML.

No download Website Updated 29 May 2011 mprfgen

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Pop 15.13
Vit 32.50

mprfgen is a multi-port memory generator that can be used for VHDL designs. It can generate either generic or Xilinx-specific (through component instantiation) multi-port memories.

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Lynis

A security audit and hardening tool.

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Fotoxx

A photo editing and collection management application.