ACL2 is a mathematical logic, programming language, and mechanical theorem prover based on the applicative subset of Common Lisp. It is an "industrial-strength" version of the NQTHM or Boyer/Moore theorem prover, and has been used for the formal verification of commercial microprocessors, the Java Virtual Machine, interesting algorithms, and so forth.
Balsa is an asynchronous circuit simulation and synthesis system. Balsa is built around the Handshake Circuits methology, and it can generate gate level netlists from high-level descriptions in the Balsa language. Both dual-rail (QDI) and single-rail (bundled data) circuits can be generated.
ChipVault is a chip development program for organizing VHDL and Verilog designs. ChipVault displays designs hierarchically and provides for rapid design navigation and editor launching. ChipVault provides hooks for performing bottom-up tasks such as launching RTL compilers, synthesis, block generation and instantiation, and includes simple to use Revision Control and Issue Tracking systems to help facilitate large group design projects with multiple designers and hundreds of design files. ChipVault is written in Perl and is small, fast, and efficient.
Confluence is a functional programming language for reactive system design, including FPGAs, ASICs, and hard-real-time software. Confluence system descriptions have a large information to linecount ratio. It is typically two to five times more compact than Verilog. Confluence can compile a single body of source code into to Verilog, VHDL, C, and NuSMV.
Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT/FST dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.
The Distributed Real-time Embedded Analysis Method (DREAM) is a tool and method for the real-time verification and performance estimation of distributed real-time embedded (DRE) systems. It focuses on the practical application of formal verification and timing analysis to real-time middleware.