JSDAI is a toolkit around STEP or ISO 10303, the STandard for the Exchange of Product model data. It supports the Express data modelling language as defined in ISO 10303-11 and provides data exchange capabilities according to ISO 10303-21 STEP-file and ISO 10303-28 STEP-XML. JSDAI Runtime is an API according ISO 10303-22, the Standard Data Access Interface (SDAI) for the Java programming language, ISO 10303-27. JSDAI Developer is for the development of Express data models, including Express-G diagrams.
UrJTAG aims to create an enhanced, modern tool for communicating over JTAG with flash chips, CPUs, and many more. It takes on the well proven openwince jtag tools code. Future plans include conversion of the code base into a library that can be used with other applications. A flexible remote communication protocol that can be used over almost any type of serial link (including TCP/IP) is currently being defined.
BOUML is a UML 2 tool box that allows you to specify and generate code in C++, Java, IDL, and PHP. BOUML is very fast and doesn't require much memory to manage several thousands of classes. BOUML is extensible, and the external tools (named plug-outs) can be written in C++ or Java, using BOUML for their definition as any other program. UML models can be exported to HTML pages, including PNG or SVG graphics.
PySTDF is a Python module which makes it easy to work with STDF (Teradyne's Standard Test Data Format). STDF is a commonly-used file format in semiconductor tests. Automated test equipment (ATE) from such vendors as Teradyne, Verigy, LTX, Credence, and others supports this format. PySTDF provides event-based stream parsing of STDF version 4, indexers that help structure the data into a more useful tabular form, and the ability to generate missing summary records or new types of derivative records. The parser architecture is very flexible and can easily be extended to support STDF version 3 and custom record types.
Pyspice is an easily extendable SPICE pre-processor written in Python to reduce simulation times with little loss in accuracy. It was inspired by John Sheahan's spicepp and developed as a modular and extensible method of pre-processing netlists. Primarily, it has been used to reduce netlists from the output of layout extraction tools. It combines parallel MOSFETs and capacitors, and optionally drops small capacitors. Planned improvements include a hierarchical namespace (e.g. .subckt/.ends and .alter blocks), more devices, and .include/.model support. Unlike other pre-processors, comments and blank lines are preserved in their relative positions. This keeps the output netlist readable for subsequent editing or processing.