RSS 25 projects tagged "Electronic Design Automation (EDA)"

Download Website Updated 25 Apr 2010 Mr Filter

Screenshot
Pop 60.91
Vit 1.87

Mr Filter is an active filter design assistant. Electrical engineers can use it to design and simulate analog active filters.

No download Website Updated 17 Sep 2008 plSTDF

Screenshot
Pop 15.30
Vit 1.00

plSTDF is a Perl module intended for working with the Terradyne STDF file format.

Download Website Updated 23 Jun 2008 JSDAI

Screenshot
Pop 17.44
Vit 1.00

JSDAI is a toolkit around STEP or ISO 10303, the STandard for the Exchange of Product model data. It supports the Express data modelling language as defined in ISO 10303-11 and provides data exchange capabilities according to ISO 10303-21 STEP-file and ISO 10303-28 STEP-XML. JSDAI Runtime is an API according ISO 10303-22, the Standard Data Access Interface (SDAI) for the Java programming language, ISO 10303-27. JSDAI Developer is for the development of Express data models, including Express-G diagrams.

Download Website Updated 08 Aug 2011 BeRTOS

Screenshot
Pop 102.24
Vit 5.20

BeRTOS is a real time operating system (RTOS) suitable for embedded platforms. It runs on many microprocessors and microcontrollers, ranging from 8-bit to 32-bit CPUs and even PCs.

Download Website Updated 12 Mar 2008 py2port

Screenshot
Pop 21.63
Vit 1.00

py2port is a tool for performing two-port and one- port analysis on linear circuits. It was developed for analyzing PCB power-distribution-systems and lossy transmission lines.

No download Website Updated 16 Mar 2007 The CBOLD Framework

Screenshot
Pop 13.08
Vit 50.89

The CBOLD framework is a set of C++ classes and related source code for capturing board-level electronic designs. It allows the designer to capture and process an electronic board-level design using a text editor (or IDE) and a C++ compiler. It provides a concise, intuitive notation for schematicless capture of board-level designs. Instead of entering a schematic into an EDA tool, the designer creates a C++ program that describes the design and the desired outputs. When the program is compiled and run, it verifies the legality of the design and writes output files (CAD layout netlist, bill of materials, FPGA constraint files, etc.) to disk. Code primarily consists of definitions of modules, which are analogous to pages of a schematic design.

Download Website Updated 21 Nov 2010 Covered

Screenshot
Pop 47.01
Vit 7.75

Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT/FST dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.

Download Website Updated 12 Aug 2006 PySTDF

Screenshot
Pop 16.61
Vit 1.00

PySTDF is a Python module which makes it easy to work with STDF (Teradyne's Standard Test Data Format). STDF is a commonly-used file format in semiconductor tests. Automated test equipment (ATE) from such vendors as Teradyne, Verigy, LTX, Credence, and others supports this format. PySTDF provides event-based stream parsing of STDF version 4, indexers that help structure the data into a more useful tabular form, and the ability to generate missing summary records or new types of derivative records. The parser architecture is very flexible and can easily be extended to support STDF version 3 and custom record types.

No download Website Updated 11 Oct 2006 pyspice

Screenshot
Pop 24.62
Vit 1.03

Pyspice is an easily extendable SPICE pre-processor written in Python to reduce simulation times with little loss in accuracy. It was inspired by John Sheahan's spicepp and developed as a modular and extensible method of pre-processing netlists. Primarily, it has been used to reduce netlists from the output of layout extraction tools. It combines parallel MOSFETs and capacitors, and optionally drops small capacitors. Planned improvements include a hierarchical namespace (e.g. .subckt/.ends and .alter blocks), more devices, and .include/.model support. Unlike other pre-processors, comments and blank lines are preserved in their relative positions. This keeps the output netlist readable for subsequent editing or processing.

Download Website Updated 28 Jul 2007 DREAM Tool

Screenshot
Pop 26.08
Vit 1.93

The Distributed Real-time Embedded Analysis Method (DREAM) is a tool and method for the real-time verification and performance estimation of distributed real-time embedded (DRE) systems. It focuses on the practical application of formal verification and timing analysis to real-time middleware.

Screenshot

Project Spotlight

DeforaOS Editor

A simple text editor for the desktop.

Screenshot

Project Spotlight

Arno's IPTABLES Firewall Script

An iptables firewall script with support for ADSL/DSL modems.