ElectricFormula is a program that can help with electronic based projects or problems. It can calculate electric power, resistance, current, or voltage. If given two of these variables as input, it can determine the other two. For example, if you want to calculate the resistance, you will have to supply the value for the electric power and current or you can supply the value of the power and voltage.
The ReliaFree Project is an alternative to commercial, proprietary reliability, availability, maintainability, and safety (RAMS) analysis software. The ReliaFree Project is an integrated suite of tools. Any number of analyses can be linked together such that an update to one module will result in all linked modules being updated appropriately. This approach provides a closed loop life-cycle with visibility into a product's performance throughout. The same database is used to store field failure data as is used to store design prediction information.
The CBOLD framework is a set of C++ classes and related source code for capturing board-level electronic designs. It allows the designer to capture and process an electronic board-level design using a text editor (or IDE) and a C++ compiler. It provides a concise, intuitive notation for schematicless capture of board-level designs. Instead of entering a schematic into an EDA tool, the designer creates a C++ program that describes the design and the desired outputs. When the program is compiled and run, it verifies the legality of the design and writes output files (CAD layout netlist, bill of materials, FPGA constraint files, etc.) to disk. Code primarily consists of definitions of modules, which are analogous to pages of a schematic design.
Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT/FST dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.
ibistools is a small set of command-line tools that aid a PCB designer working with IBIS models. It currently consists of a full IBIS v4.1 parser and an IBIS to SPICE translator. IBIS (I/O Buffer Information Specification) is a standard, human-readable, machine-readable format for publishing IC specifications.
PySTDF is a Python module which makes it easy to work with STDF (Teradyne's Standard Test Data Format). STDF is a commonly-used file format in semiconductor tests. Automated test equipment (ATE) from such vendors as Teradyne, Verigy, LTX, Credence, and others supports this format. PySTDF provides event-based stream parsing of STDF version 4, indexers that help structure the data into a more useful tabular form, and the ability to generate missing summary records or new types of derivative records. The parser architecture is very flexible and can easily be extended to support STDF version 3 and custom record types.
Pyspice is an easily extendable SPICE pre-processor written in Python to reduce simulation times with little loss in accuracy. It was inspired by John Sheahan's spicepp and developed as a modular and extensible method of pre-processing netlists. Primarily, it has been used to reduce netlists from the output of layout extraction tools. It combines parallel MOSFETs and capacitors, and optionally drops small capacitors. Planned improvements include a hierarchical namespace (e.g. .subckt/.ends and .alter blocks), more devices, and .include/.model support. Unlike other pre-processors, comments and blank lines are preserved in their relative positions. This keeps the output netlist readable for subsequent editing or processing.