TTA-based Co-design Environment (TCE) is a toolset that provides a complete co-design flow from C programs down to synthesizable VHDL and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network.
Resistors is a program to calculate the most suitable E-series resistors for voltage dividers or for generating other values by putting two resistors in parallel. It is especially useful for selecting resistor values for the voltage dividers used in variable voltage regulators. In effect, the voltage in the middle of the divider is known, and you want to achieve a regulated voltage (the top value).
Spice+ is a general-purpose circuit simulation program based directly on Spice3f5. Its main purpose is to allow university students and other interested people to simulate their circuits without buying expensive simulation programs or being limited by free trial versions of such software. Since source code is available, students or researchers can use it as a basis for new models and algorithms.
UrJTAG aims to create an enhanced, modern tool for communicating over JTAG with flash chips, CPUs, and many more. It takes on the well proven openwince jtag tools code. Future plans include conversion of the code base into a library that can be used with other applications. A flexible remote communication protocol that can be used over almost any type of serial link (including TCP/IP) is currently being defined.
KiCad EDA is software for the creation of electronic schematic diagrams and printed circuit board artwork. It is a set of four programs and a project manager: Eeschema (schematic entry), Pcbnew (a board editor), Gerbview (a Gerber viewer (photoplotter documents)), and Cvpcb (a footprint selector for components used in the circuit design). Kicad is the project manager. It includes a 3D visualization feature.
Scheture is a hierarchical schematic capture system with built-in netlisters for Spice and Verilog. It has built-in plotting for Postscript, HP PCL and HP GL/2 printers and plotters. It includes a set of symbol primitives, and allows user-defined symbol primitives to allow for extensive customization of primitive properties. The system supports wire buses and iterated instances. The system also supports global pins and implicitly connected pins on a specific sheet. Supported platforms include Solaris and Linux (32- and 64-bit).
Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT/FST dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.