RSS 10 projects tagged "Electronic Design Automation (EDA)"

Download Website Updated 16 Jul 2012 DOLPHIN SLED

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Pop 61.81
Vit 6.82

DOLPHIN SLED is a hierarchical schematic entry solution with graphic linking of components, hierarchical configuration of the netlist, and multi-language netlisting (SPICE, Verilog, VHDL-AMS, etc.). Interoperability with other schematic entry tools, particularly the ECS family (including Synario, Cohesion, and Laker-AMS) is ensured for capitalizing on legacy designs and cooperative work. Interoperability is ensured through standard design exchange formats (EDIF2) and scriptability for customization.

No download Website Updated 18 May 2012 Scheture

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Pop 66.95
Vit 5.79

Scheture is a hierarchical schematic capture system with built-in netlisters for Spice and Verilog. It has built-in plotting for Postscript, HP PCL and HP GL/2 printers and plotters. It includes a set of symbol primitives, and allows user-defined symbol primitives to allow for extensive customization of primitive properties. The system supports wire buses and iterated instances. The system also supports global pins and implicitly connected pins on a specific sheet. Supported platforms include Solaris and Linux (32- and 64-bit).

No download Website Updated 10 Jan 2014 Slam-Edit

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Pop 136.92
Vit 26.73

Slam is a mature IC Layout editor with the ability to edit very large designs (such as stream files larger than 10GB). Novel features include threading for redraw, support for displaying on multiple X servers simultaneously, and a Tcl interface to the database for user extensibility. The system is a library based system with multi-user support. Programmable structures (P-Cells) are available in Tcl. The editor includes gds input and output.

Download Website Updated 05 Sep 2004 nMicrocoder

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Pop 32.02
Vit 1.00

nMicrocoder is an ncurses EDA tool to write microcode. Basically, it is a stripped down spreadsheet program that lets you fill a table with "0", "1", and "-", and gives you compile-ready verilog code in return. It was written as an alternative to full spreadsheet programs. It is known to run on Linux, IRIX, and Solaris, unless ncurses 5.3 is installed.

No download Website Updated 11 Sep 2004 Alliance CAD System

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Pop 88.66
Vit 1.74

Alliance CAD System is a set of EDA tools and portable cell libraries for VLSI design. It covers a wide range of the standard design flow (from VHDL up to layout). It includes a VHDL simulator, RTL synthesis tools, place and route tools, netlist extractor, DRC, and a layout editor.

No download Website Updated 08 Jul 2003 GraphPak for Qt

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Pop 39.56
Vit 1.00

GraphPak is a programming library of 2D and 3D charting objects for the Qt toolkit. It provides software developers with a set of C++ objects to easily create charts or graphs that aid in the visual presentation of technical and business data. This release includes Bar, Line, Pie, Ring, Area, Hi-Lo, Box and Whisker, and Polar charts. It is based on the KD Chart product from Klarälvdalens Datakonsult AB.

Download Website Updated 12 Nov 2002 ChipVault

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Pop 57.06
Vit 2.33

ChipVault is a chip development program for organizing VHDL and Verilog designs. ChipVault displays designs hierarchically and provides for rapid design navigation and editor launching. ChipVault provides hooks for performing bottom-up tasks such as launching RTL compilers, synthesis, block generation and instantiation, and includes simple to use Revision Control and Issue Tracking systems to help facilitate large group design projects with multiple designers and hundreds of design files. ChipVault is written in Perl and is small, fast, and efficient.

Download Website Updated 11 Feb 2007 SoC GDS

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Pop 57.45
Vit 5.67

SoC GDS is a platform for enabling hierarchical SoC integration and verification across traditional EDA frameworks based on Virtual Components per the VSIA guidelines. It is also a fast viewer and processor for native GDSII files. It encompasses a set of powerful functions allowing automatic cell renaming, grid verifications, GDS II files merging (AND), physical comparison (XOR), hierarchy modifications, and conversion to text format.

Download Website Updated 24 Dec 2004 HDLmaker

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Pop 56.39
Vit 1.19

HDLmaker generates hierarchical Verilog and VHDL code, PCB netlists, simulation and synthesis scripts/projects/make files, and schematics. It can translate Verilog/VHDL and HDLmaker projects into HTML, including extensive hyperlinking between the modules. It can also translate PADS PCB netlists into Verilog and VHDL and can do some simple VHDL to Verilog translations. HDLMaker synplifies the development of complex FPGAs and ASICs, and has extensive support for most Xilinx FPGAs.

No download Website Updated 21 Jun 2010 ngspice

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Pop 77.77
Vit 5.66

Ngspice is a mixed-level/mixed-signal circuit simulator based on three open source software packages: Spice3f5, Cider1b1, and Xspice. Spice3 is the most famous and widely used circuit simulator. Cider is mixed-level simulator that includes Spice3f5 and adds DSIM, a device simulator. Cider couples the circuit level simulator to the device simulator to provide greater simulation accuracy (at the expense of greater simulation time). Xspice is an extension to Spice3 that provides code modeling support and simulation of digital components through an embedded event driven algorithm.

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A Super Mario Bros. game.