ibistools is a small set of command-line tools that aid a PCB designer working with IBIS models. It currently consists of a full IBIS v4.1 parser and an IBIS to SPICE translator. IBIS (I/O Buffer Information Specification) is a standard, human-readable, machine-readable format for publishing IC specifications.
PySTDF is a Python module which makes it easy to work with STDF (Teradyne's Standard Test Data Format). STDF is a commonly-used file format in semiconductor tests. Automated test equipment (ATE) from such vendors as Teradyne, Verigy, LTX, Credence, and others supports this format. PySTDF provides event-based stream parsing of STDF version 4, indexers that help structure the data into a more useful tabular form, and the ability to generate missing summary records or new types of derivative records. The parser architecture is very flexible and can easily be extended to support STDF version 3 and custom record types.
Electronic Engineering Tool is a Web-based tool that includes an electronic formula calculator and converter functions. It very useful when working with electronics, both for engineers and amateurs. For example, it includes converters for dBm-to-Watt and Fahrenheit-to-Celsius, and it can calculate Ohm's law, filters, thermal resistant C/W, SWR, coil inductance, capacitor capacity, and more.
Platform Independent Petri Net Editor (PIPE) creates and analyses Petri Nets quickly, efficiently, and effectively. A key design feature is the modular approach adopted for analysis, enabling new modules to be written easily and powerfully, using built-in data layer methods for standard calculations. Six analysis modules are provided, including Invariant Analysis, State-Space Analysis (deadlock, etc.), and Simulation Analysis and Classification. PIPE adheres to the XML Petri net standard (PNML). The file format for saving and loading Petri Nets is extensible through the use of XSLT, the default being PNML.
asfpga is an assembler written for use in FPGA design. It can be easily modified for a particular instruction set. The ultimate goal of this software is to allow a FPGA designer to easily write assembly code for a custom instruction set. The current version allows you to create a listing file, a memory dump file which can be used in debugging HDL code using $readmemh() or equivalent routine, and a binary file which can be used to program an EPROM.