JTAGTest is an IEEE 1149.1 JTAG Boundary scan tester for embedded designers, production houses, and service companies. It provides a significant aid for PCB debugging, prototyping, testing, and repairing. Using an IEEE 1149.1 (JTAG) boundary-scan, the device pin signals or internal signals can be monitored in real-time without interfering with normal device operation, and you can change pin state manually. It runs under Wine on 32-bit Linux distributions using special Linux support libraries, which are included in the distribution.
JSDAI is a toolkit around STEP or ISO 10303, the STandard for the Exchange of Product model data. It supports the Express data modelling language as defined in ISO 10303-11 and provides data exchange capabilities according to ISO 10303-21 STEP-file and ISO 10303-28 STEP-XML. JSDAI Runtime is an API according ISO 10303-22, the Standard Data Access Interface (SDAI) for the Java programming language, ISO 10303-27. JSDAI Developer is for the development of Express data models, including Express-G diagrams.
Spice+ is a general-purpose circuit simulation program based directly on Spice3f5. Its main purpose is to allow university students and other interested people to simulate their circuits without buying expensive simulation programs or being limited by free trial versions of such software. Since source code is available, students or researchers can use it as a basis for new models and algorithms.
BOUML is a UML 2 tool box that allows you to specify and generate code in C++, Java, IDL, and PHP. BOUML is very fast and doesn't require much memory to manage several thousands of classes. BOUML is extensible, and the external tools (named plug-outs) can be written in C++ or Java, using BOUML for their definition as any other program. UML models can be exported to HTML pages, including PNG or SVG graphics.
FerFT is a multi-purpose spectral analyzer based on the successive Fourier transformation method. It features an input signal monitor which can sample input signals through a microphone with various sample rates and show them graphically on the panel. It also lets you calculate power spectra successively along with sampled input signals and show them graphically on the panel. Finally, it provides a filter to modify spectra and regenerate signals from them.
The CBOLD framework is a set of C++ classes and related source code for capturing board-level electronic designs. It allows the designer to capture and process an electronic board-level design using a text editor (or IDE) and a C++ compiler. It provides a concise, intuitive notation for schematicless capture of board-level designs. Instead of entering a schematic into an EDA tool, the designer creates a C++ program that describes the design and the desired outputs. When the program is compiled and run, it verifies the legality of the design and writes output files (CAD layout netlist, bill of materials, FPGA constraint files, etc.) to disk. Code primarily consists of definitions of modules, which are analogous to pages of a schematic design.