The IBM Full-System Simulator has been developed and refined in conjunction with several large-system design projects built upon the IBM Power Architecture. As an execution-driven, full-system simulator, the IBM Full-System Simulator facilitates the experimentation and evaluation of a wide variety of system components for core IBM initiatives, such as the STI Cell and the IBM PERCS projects. The IBM Full-System Simulator for PowerPC 970 enables development teams both within and outside IBM to simulate a PowerPC 970 system in order to develop and enhance application support for this platform.
Xnetintf is an X Windows application that manages network interfaces. The current interface state is depicted through a series of bitmaps, and a mouse click in the window initiates a state transition. Xnetintf uses a per-interface configuration file to supply commands that check and toggle state, as well as a program to run after the state change completes. A command line interface is also supported.
ATG Dynamo integration for JBuilder is a JBuilder 5 plugin that makes it easy to deploy J2EE applications to the ATG Dynamo Application Server version 5.1 (DAS). It can be installed and run with the other JBuilder 5 plugins such as BEA WebLogicServer 5.1, BEA WLS 6, IBM WebSphere 3.5, Borland AS 4.5, etc.
Userexitd for TSM is a configurable handler for Tivoli Storage Manager events. It allows an administrator to filter events using regular expressions and run various actions for TSM events, such as sending mail and SNMP traps, writing messages into syslog, and running scripts and programs. This software consists of two parts: a simple shared library (userexit.so), which is dynamically linked to the TSM Server as a user exit and communicates using a socket with the userexitd daemon, which runs as a separate service. The daemon is configured with an XML configuration file.
The FoCs (short for Formal CheckerS, pronounced "fox") property checkers generator is a productivity tool for automatic generation of simulation monitors from formal specifications. It aids chip designers and verification engineers in the complex, costly task of verifying chip designs before submitting them to manufacturing.