Release Notes: This release comes with an interactive GNU/Octave interface. Syntax highlighting for Octave, Verilog-HDL, and Verilog-A syntax has been added. Pre-compiled VHDL modules and libraries made from user-written VHDL code are supported now. There are several new components, such as transistor models NIGBT, HICUM L2 v2.24, HICUM L0 v1.2g and HICUM L0 v1.3, tunnel diode, ideal coupled transmission line, and an ideal hybrid. The equation solver now has EMI receiver functionality implemented. The qucsconv command line data converter supports Matlab v4 as an export file format.
Release Notes: This release comes with new translations into Arabic and Czech, model libraries for MOSFETs regulators, varistors, and ideal components, and many new primitive components such as EPFL-EKV NMOS/PMOS V2.6, HICUM L0 v1.2, and numerous digital primitives. Passing parameters to Verilog-HDL and VHDL subcircuits and typed generic parameters of VHDL files are now supported as well as arbitrary in/out signals. The Qucs-Converter tool now allows you to translate existing HICUM models into library elements as well as the translation of polynomial C's and L's and F, H, E, and G polynomial SPICE sources.
Release Notes: This release comes with a few new components, i.e., diac, triac, thyristor, logarithmic amplifier, HICUM L0 v1.12, potentiometer, equation defined RF device, and MESFET (Curtice, Statz, TOM-1, and TOM-2). The Qucs-Transcalc tool also contains synthesis and analysis of coplanar line types. Printing under Win32 has finally been fixed. Support for sub- and super-script in graphical text paintings has been added. Last but not least, versions of PlotVs() with 3 or more arguments have been added to the equation solver capabilities.
Release Notes: This release comes with some new components, i.e. file-based current and voltage sources, a modular operational amplifier, and the HICUM L2 v2.22 device model. In equations, immediate vectors and matrices are allowed as well as engineering notation of numbers, and some more functions have been added (random, srandom, StabFactor, and StabMeasure). Touchstone files can be exported and CSV files can be imported using the command line data converter QucsConv.
Release Notes: This release comes with a translation into Ukrainian, a selectable preprocessor in the SPICE component, and two new components (exponential voltage and current source). Libraries can now contain analogue as well as digital subcircuits. Analogue modelling is substantially strengthened by symbolically defined devices. The list of available functions in the equation solver has been extended to support more functions, logical and rational operators, and the ternary ?: construct. Pure digital simulations can be also performed by Verilog-HDL as an alternative to VHDL.
Release Notes: This release comes with two new translations into Czech and Catalan, subcircuit parameters and equations in subcircuits. Some new components have been added, including the device models for HICUM L2 v2.1 and FBH HBT using a Verilog-AMS interface. Subcircuit parameters have been implemented, which can be sweep parameters and constants as well as equation variables. Equation variables can now also be used in component properties and input parameters of components in equations. The model for the non-ideal microstrip junction has been implemented.
Release Notes: This release comes with an attenuator synthesis application, support for nine-valued VHDL logic, and user libraries that can be created from subcircuits. Steps have been taken to allow circuit optimization using ASCO in one of the next releases. Data files such as Touchstone, CITIfiles, VCD, and MDL can be imported, and CSV files can be exported. The simulation backend is now supporting the SVD algorithm as an equation system solver, initial conditions (transient analysis) for L and C are available, and the equation solver has a new function signum.
Release Notes: This release comes with a Russian translation. The digital simulation abilities have been improved by a VHDL text editor. There are new components such as a coaxial line, a differential voltage probe, a switch, AM- and PM-modulators, and a relais. The simulation backend supports delay times of digital components and controlled sources during the transient analysis. There is a time-domain model of the ideal transmission line. Many new functions have been added to the equation solver.
Release Notes: Digital simulations using FreeHDL are now possible. The new release includes a Turkish translation and truth table and timing diagrams. Matching circuits can be created and there is a dialog for changing the properties of several components at once. The filter synthesis tool now supports some additional filter types, many new models were added to the component libraries, and the DC bias can be annotated in the schematic. Digital gates, correlated noise sources, an ideal coupler, and mutual inductors are now supported.
Release Notes: Qucs is now known as "Quite Universal Circuit Simulator". The GUI additionally supports text painting rotations in subcircuit symbols, and Latex-like mnemonics (e.g. \tau) in graphic texts and diagram labels. A library manager that includes some transistors, diodes, and substrates was added. Several small improvements and bugfixes have been incorporated. The simulation backend supports some new functions in the equation solver: unwrap(), rad2deg(), and deg2rad(). A heavy bug in the non-linear operational amplifier model has been fixed.