JHDL is a set of FPGA CAD tools which allows the user to design the structure and layout of a circuit, debug the circuit in simulation, netlist, and interface with backend tools for synthesis, etc. It is an exploratory attempt to identify the key features and functionality of good FPGA tools.
|Tags||Scientific/Engineering Electronic Design Automation (EDA)|
|Operating Systems||OS Independent|
Release Notes: Enhanced floating point packages have been added. Minor bugs in Netlists and other JHDL features have been addressed.
Release Notes: Class interdependencies have been reduced and several minor bugs have been fixed. Stepping the clock in hardware when doing debugging has been significantly been improved.
Release Notes: Since 0.3.20, a first cut of the XC9000 library and Techmapper have been released. This is still alpha quality, but it is adequate for programming the Xess PLD. Many bugs and clarifications were made in the Viewers classes. An indemnity clause was dropped from the license to allow persons who cannot indemnify themselves to release the software.
Release Notes: CVT and several visualization tools were improved. Optimized versions for Virtex and VirtexII wide and, ors, nands and nors were fixed. Documentation was widely enhanced and made more extensive.
Release Notes: The UI for simulation is moving from Jab to a user design driven model with the Circuit Visualization Tool. This is the first public release with government approval in the license. The build process has been improved.