Release Notes: This release delivers increased logic simulation speed, both at gate level and at behavioral level, along with a number of fixes.
Release Notes: This release provides major improvements, including a Graphical User Interface for Trading-off Accuracy and Rapidity (GUITAR), an add-on for logic power consumption estimation, extended compliance with Verilog-AMS and VHDL-AMS standards, and unleashed SPICE and VHDL-AMS mixity allowing any hierarchical instantiations.
Release Notes: Many bugfixes and display cleanups. Support has been added for 64-bit values and jitter.
Release Notes: This release provides enhanced data extractors, output summaries, toggle tests, dispersion displays and the like, as well as the patented SWIFT algorithm, allowing time-domain simulations to be performed two to three times faster on transistor-based circuits, with no loss of accuracy.
Release Notes: This release provides the Berkeley BSIM4v3 transistor model, including stress effects.
Release Notes: This release now supports new types and syntaxes of voltage and current sources for compatibility with HSPICE netlists. VHDL-AMS units can now be directly instantiated in SPICE sub-circuits.
Release Notes: This release improves the netlist parsing for better compatibility with PSpice netlists. It implements reporting of environment variables to circuit load report in order to simplify the debugging of environment related issues when using environment variables in the pattern file or in library files.
Release Notes: Device model approximation has been implemented using a combination of a simplified device model (fast evaluation) and a full device model (accurate evaluation) to accelerate transient analysis of MOS transistors. This release improves mixed-language hierarchical instantiation and implements the instantiation of Verilog modules in VHDL architectures. Architecture-specific checks for equation count vs. quantity count checks in VHDL-AMS have been implemented.
Release Notes: This release adds support of global SPICE nets in Verilog descriptions so that global nets, defined using the .GLOBAL directive, can be used in Verilog modules without having been explicitly defined in Verilog or specified in the module inputs/outputs.
Release Notes: This release implements memory optimizations for large SPICE circuits as well as major speed improvements for simulation of second and third order VHDL-AMS models, which is particularly important for complex MEMS designs. This release also provides co-simulation with SystemC models, and graphic interface improvements such as a configurable toolbar.