Release Notes: The release implements multi-core aware equation evaluation for SPICE device models to speed up the analog simulation, automatic detection of multiple operating points to ensure design operation for all bias points, simplified use of audio data files to drive analog simulation, time precision handling for VHDL and VHDL-AMS simulations longer than 9223 seconds, an enhanced debugger with expression watches, expression breakpoints and breakpoint actions, and user selection of which SPICE device and model parameters to output to the operating-point file.
Release Notes: A number of fixes to simulator control file parsing for mixed language netlists along with other simulator kernel corrections.
Release Notes: The release implements enhanced ease of setup with a simulator control file for analog and logic designers, a streamlined graphic user interface with reworked menu bar and enriched tool bars, integrated Power-Up analysis for transient ramp-up of circuit power supplies, accelerated automatic operating-point searching, bias point saving during transient analysis, noise analysis for Verilog-A models, encryption of SPICE libraries, and optimized on-the-fly SDF annotation to reduce memory consumption during circuit elaboration.
Release Notes: This release has a number of SPICE, Verilog, VHDL, and VHDL-AMS related bugfixes and minor improvements.
Release Notes: This release implements some minor improvements and fixes a number of issues, including analog simulation time regression, Verilog and VHDL-AMS parsing and simulation defects, and power consumption analysis-related defects.
Release Notes: Numerous enhancements including hierarchical analog power computing, computing and tracing of analog net resistive and capacitive impedance, and PSP (Penn State and Philips) and EKV3 MOSFET models.
Release Notes: A simulation speed regression related to the BSIM3 and BSIM4 models was corrected along with a number of other bugfixes.
Release Notes: The release delivers an interactive debugger with break points, step by step and event back trace for source level debugging of HDL-AMS descriptions, phase-noise extraction on long term Jitter, a SPICE inductance model with magnetic core as well as cosimulation of analog and mixed-signal blocks with MATLAB/Simulink.
Release Notes: This release delivers many enhancements for increased productivity and interoperability, including HDL-AMS code coverage analysis, a logic trace dialog with a hierarchical tree view, CSDF waveform format output, import and export of VCD (Value Change Dump) files for Verilog / VHDL, DC and small-signal dispersion sensitivity analysis, and the BSIM4v5 model with Well Proximity Effect.
Release Notes: A number of bugfixes and improvements, including the frequently requested ability to use precompiled VHDL and VHDL-AMS libraries without compilation of corresponding source files.