Release Notes: This release improves the loading runtime of large Verilog files with an important number of ports and implements support of the .MALIAS directive to assign an alias to a model or sub-circuit name, along with a number of minor corrections.
Release Notes: This release implements nested sweeping, sweeping with two or more parameters at the same time, an improved the time step predictor to accelerate SPICE transient simulations, coverage analysis support for Verilog question-colon operator and for VHDL concurrent assignment statements, the SPICE model BSIM-CMG v106.1, and an optimizer targeting design of analog blocks.
Release Notes: This release improves multi-threading of all SPICE models to increase transient simulation speed, implements support of Verilog pulse control capabilities, and provides a number of minor fixes and corrections.
Release Notes: This release implements major improvements to instantiation of behavioral models (HDL/HDL-AMS) in SPICE netlists with mixed macro-models, better multi-threading capabilities to increase transient simulation speed of analog designs, Monte Carlo and Sweep analyses on logic designs, a domain coloring viewer with phase and magnitude viewing, .MODEL for Verilog-A foundry models, .NRT for equivalence checking between waveforms, and the ability to define a directory to redirect all output files.
Release Notes: This release implements major improvements among which domain coloring for a first approximation of the pole/zero locations, a .PZ directive for pole/zero analysis, support of .wav files as ouput of logic designs, and CCS segmentation extraction processing functions.
Release Notes: This release implements reading of .wav formats in logic for audio based test benches and Verilog language compliance improvements, along with a number of minor corrections.
Release Notes: This release delivers support for VHDL 1076-2008 protect tool directives and Verilog 1364-2005 protected envelopes allowing exchange of HDL descriptions in which portions are encrypted. A number of minor fixes and improvements are also included.
Release Notes: This release implements major improvements including extended Assertion-Based Verification (ABV) capabilities with SystemVerilog Assertions (SVA), compliance with Verilog-AMS wreal for Real Valued Modeling (RVM), increased Verilog-HDL and Verilog-A language compliance, improved HSpice compatibility with .IF,.ELSIF,.ELSE,.ENDIF conditional generate statements, and accelerated circuit loading, Monte Carlo and Sweep analysis.
Release Notes: This release delivers a significant speed increase for the loading of SPICE library files and circuits, particularly significant when accessing files on slow network disks. A number of minor enhancements and fixes were also made.
Release Notes: This release implements major improvements including linear loop stability (.LSTB) and data sampling noise (.SAMPLE) analyses, increased Verilog-A simulation performance support for analog functions for behavioral modeling, extended HSPICE compliance with the support of .ALTER and .DEL LIB directives, and device analysis capabilities with interactive editing of SPICE device parameters and tracing of device characteristics.