Release Notes: This release provides a number of minor fixes and enhancements, including HSPICE compatibility improvements, as well as Verilog and VHDL language compliance corrections.
Release Notes: This release provides Imbalance Locate analysis using dispersion data in foundry models, an enhanced Sweep dialog for multiple parameter sweeping, an optimizer for multiple analysis optimizations, accelerated transient noise simulations with integrated transistor level multi-threading, improved back-annotation file for schematic editors, auto-completion for HDL languages based on templates, and integrated help with tooltip display of expected values and parameters for Verilog functions.
Release Notes: This release provides a brand-new and efficient waveform viewer, for analysis of mixed-signal simulation results, as well as a styled user interface, enabling users to access and configure more easily the powerful analyses provided by the mixed-signal simulator. This release also integrates the standard BSIM SOI compact model for Silicon-On-Insulator circuit design.
Release Notes: This release improves the loading runtime of large Verilog files with an important number of ports and implements support of the .MALIAS directive to assign an alias to a model or sub-circuit name, along with a number of minor corrections.
Release Notes: This release implements nested sweeping, sweeping with two or more parameters at the same time, an improved the time step predictor to accelerate SPICE transient simulations, coverage analysis support for Verilog question-colon operator and for VHDL concurrent assignment statements, the SPICE model BSIM-CMG v106.1, and an optimizer targeting design of analog blocks.
Release Notes: This release improves multi-threading of all SPICE models to increase transient simulation speed, implements support of Verilog pulse control capabilities, and provides a number of minor fixes and corrections.
Release Notes: This release implements major improvements to instantiation of behavioral models (HDL/HDL-AMS) in SPICE netlists with mixed macro-models, better multi-threading capabilities to increase transient simulation speed of analog designs, Monte Carlo and Sweep analyses on logic designs, a domain coloring viewer with phase and magnitude viewing, .MODEL for Verilog-A foundry models, .NRT for equivalence checking between waveforms, and the ability to define a directory to redirect all output files.
Release Notes: This release implements major improvements among which domain coloring for a first approximation of the pole/zero locations, a .PZ directive for pole/zero analysis, support of .wav files as ouput of logic designs, and CCS segmentation extraction processing functions.
Release Notes: This release implements reading of .wav formats in logic for audio based test benches and Verilog language compliance improvements, along with a number of minor corrections.
Release Notes: This release delivers support for VHDL 1076-2008 protect tool directives and Verilog 1364-2005 protected envelopes allowing exchange of HDL descriptions in which portions are encrypted. A number of minor fixes and improvements are also included.