Projects / Covered

Covered

Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT/FST dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.

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RSS Recent releases

  •  21 Nov 2010 20:29

    Release Notes: This release adds support for FST dumpfile parsing, language enhancements, and bugfixes.

    •  25 Mar 2010 11:21

    Release Notes: Bugfixes and enhancements for Verilog language support.

    •  25 Oct 2009 09:29

      Release Notes: This is a bugfix release.

      •  26 Aug 2009 11:45

      Release Notes: This is a bugfix release.

      •  03 Aug 2009 05:23

      Release Notes: Several performance improvements were added for the new inlined code coverage flow. This release also contains bugfixes for inlined runs.

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