All releases of Confluence System Design Language

  •  18 Feb 2005 04:43
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    Release Notes: This release includes the initial FNF C model generator that enables a compilation path from Confluence to C. New features include a new simulator data structure, which enables running multiple simulation models at once, and provides access to all hierarchical named signals in a design. This release also includes the Icarus Verilog FNF generator, providing a path from Verilog to C, VHDL, NuSMV, and JHDL.

    •  02 Feb 2005 04:41
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      Release Notes: Adds a new code generator that allows it to compile into JHDL, a Java-based hardware description language.

      •  09 Jan 2005 09:57
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        Release Notes: In this release, the compiler backend was integrated with FNF, forming a clean partition between language evaluation and model generation.

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